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wide supply dual, 17 mhz, rail-to-rail fet input amplifier data sheet ad823a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features single-supply operation output swings rail-to-rail input voltage range extends below ground single-supply capability from 3 v to 36 v high load drive capacitive load drive of 470 pf (g = +1, 25% overshoot) linear output current of 40 ma, 0.5 v from supplies excellent ac performance on 2.6 ma/amplifier ?3 db bandwidth of 17 mhz, g = +1 325 ns settling time to 0.01% (2 v step) slew rate of 30 v/s low distortion: ?108 dbc at 20 khz (g = ?1, r l = 2 k) good dc performance 700 v maximum input offset voltage 1 v/c offset voltage drift 25 pa maximum input bias current low noise: 14 nv/hz at 10 khz no phase inversion with inputs to the supply rails applications photodiode preamps active filters 12-bit to 16-bit data acquisition systems medical instrumentation precision instrumentation general description the ad823a is a dual precision, 17 mhz, jfet input op amp manufactured in the extra fast complementary bipolar (xfcb) process. the ad823a can operate from a single supply of 3 v to 36 v or from dual supplies of 1.5 v to 18 v. it has true single-supply capability with an input voltage range extending below ground in single-supply mode. output voltage swing extends to within 20 mv of each rail for iout 100 a, providing outstanding output dynamic range. it also has a linear output current of 40 ma, 0.5 v from the supply rails. an offset voltage of 700 v maximum, an offset voltage drift of 1 v/c, and typical input bias currents of 0.3 pa provide dc precision with source impedances up to 1 g. the ad823a provides 17 mhz, ?3 db bandwidth, and a 30 v/s slew rate with a low supply current of only 2.6 ma per amplifier. it also provides low input voltage noise of 14 nv/hz and ?108 db sfdr at 20 khz. the ad823a has low input capacitances (0.6 pf differ- ential and 1.3 pf common mode) and drives more than 500 pf of direct capacitive load as a follower. this lets the amplifier handle a wide range of load conditions. connection diagram ad823a out1 +in2 ?in2 out2 +v s ?in1 +in1 ?v s 1 2 3 4 8 7 6 5 09439-001 figure 1. 8-lead soic 09439-102 out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 out2 7 ?in2 6 +in2 5 ad823a top view (not to scale) figure 2. 8-lead msop 200s/div 500mv/div 0v 3.0v 1.5v 0 9439-049 v s = 3v c l = 50pf g = +1 figure 3. output swing, +v s = +3 v, g = +1 this combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile ampli- fier for applications such as adc drivers, high speed active filters, and other low voltage, high dynamic range systems. the ad823a is available over the industrial temperature range of ?40c to +85c and is offered in an 8-lead soic package and an 8-lead msop package.
ad823a data sheet rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? connection diagram ....................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 5 v operation ............................................................................... 3 ? 3.3 v operation ............................................................................ 4 ? 15 v operation ........................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................8 ? theory of operation ...................................................................... 14 ? output impedance ..................................................................... 14 ? applications information .............................................................. 15 ? input characteristics .................................................................. 15 ? output characteristics............................................................... 15 ? wideband photodiode preamp ................................................ 16 ? active filter ................................................................................. 18 ? maximizing performance through proper layout ............... 19 ? outline dimensions ....................................................................... 20 ? ordering guide .......................................................................... 20 ? revision history 6/12rev. a to rev. b added text to absolute maximum ratings section .................... 6 changes to equation 8 ................................................................... 18 5/12revision a: initial version
data sheet ad823a rev. | page 3 of 20 specifications 5 v o peration t a = 25 c, +v s = 5 v, r l = 2 k? to 2.5 v, unless ot herwise noted . table 1. parameter conditions min typ max unit dynamic performance ? 3 db bandwidth g = +1, v o ut 0.2 v p -p 14.1 17 mhz full power response v o ut = 2 v p -p 4.8 mhz slew rate g = ? 1, v o ut = 4 v step 25 30 v/s settling time to 0.1% g = ?1, v o ut = 2 v step 240 ns to 0.01% g = ?1, v o ut = 2 v step 325 ns noise/distortion performance input voltage noise f = 10 khz 14 nv/hz input curr ent noise f = 1 khz 1 fa/hz harmonic distortion (sfd r) v o ut = 2 v p - p, f = 20 khz , g = ?1 , r f = r g = 4 k ?108 dbc v out = 2 v p - p, f = 20 khz, g = + 1 , r l = 1 k ? 99 dbc crosstalk f = 1 khz r l = 5 k ?1 23 db f = 1 mhz r l = 5 k ?77 db dc performance initial offset 0.12 0.7 mv maxi mum offset o ver te mperature 0.2 1.3 mv offset drift 1 v/c input bias current v cm = 0 v to 4 v 0.3 25 pa at t max v cm = 0 v to 4 v 10 25 pa input offset current 0.3 20 pa at t max 3.5 pa open - loop gain v o ut = 0.2 v to 4 v, r l = 2 k 40 17 5 v/mv t min to t max 25 v/mv input characteristics input common - mode voltage range ? 0.2 to +3 ? 0.2 to +3.8 v input resistance 10 13 input capacitance differential mode 0.6 pf common mode 1.3 pf common - mode rejection ratio v cm = 0 v to 3 v 60 73 db output charac teristics output voltage swing i l = 100 a 0.00 9 to 4.98 v i l = 2 ma 0.026 to 4.9 6 v i l = 10 ma 0.097 to 4. 88 v linear output current v out = 0.5 v to 4.5 v 40 ma short - circuit current sourcing to 2.5 v 50 ma sinki ng to 2.5 v 101 ma capacitive load drive g = +1 500 pf power supply operating range 3 36 v quiescent current t min to t max , total 5.1 5.7 ma power supply rejection ratio v s = 5 v to 15 v, t min to t max 70 94 db b
ad823a data sheet rev. | page 4 of 20 3.3 v o peration t a = 25 c, +v s = 3.3 v, r l = 2 k? to 1.65 v, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ? 3 db bandwidth g = +1, v o ut 0.2 v p -p , v cm = 0.65 v 13.8 17.3 mhz ful l power response v o ut = 2 v p -p 3.7 mhz slew rate g = ?1, v o ut = 2 v step, v cm = 0.65 v 18 23 v/s settling time to 0.1% g = ?1, v o ut = 2 v step 350 ns to 0.01% g = ?1, v o ut = 2 v step 460 ns noise/distortion performance input voltag e noise f = 10 khz 1 4 nv/hz input current noise f = 1 khz 1 fa/hz harmonic distortion (sfdr) v o ut = 2 v p - p, f = 20 khz , g = ?1 , r f = r g = 4 k ?108 dbc v out = 2 v p - p, f = 20 khz, g = + 1, r l = 100 ?70 dbc crosstalk f = 1 khz r l = 5 k ? 12 3 db f = 1 mhz r l = 5 k ?77 db dc performance ini tial offset 0.14 1 mv maximum offset o ver temperature 0.3 1.8 mv offset drift 1 v/c input bias current v cm = 0 v to 2 v 0.3 25 pa at t max v cm = 0 v to 2 v 10 25 pa input of fset current 0.3 20 pa at t max 3.5 p a open - loop gai n v o ut = 0.2 v to 2 v, r l = 2 k 16 63 v/mv t min to t max 14 v/mv input characteristics input common - mode voltage rang e ? 0.2 to +1 ? 0.2 to +1.8 v input resistance 10 13 input capa citance differential mode 0.6 pf common mode 1.3 pf common - mode rejection ratio v cm = 0 v to 1 v 54 71 db output characteristics output voltage swing i l = 100 a 0.006 to 3.28 v i l = 2 ma 0.04 to 3.2 6 v i l = 10 ma 0.093 to 3.18 v linear output current v out = 0.5 v to 2.5 v 40 ma short - circuit current sourcing to 1.5 v 44 ma sinking to 1.5 v 86 ma capacitive load drive g = +1 500 pf power supply operating range 3 36 v quiescent current t min to t max , t otal 5.0 5.7 ma power supply rejection ratio v s = 3.3 v to 15 v, t min to t max 70 80 db b
data sheet ad823a rev. | page 5 of 20 15 v operation t a = 25 c, v s = 15 v, r l = 2 k? to 0 v, unless otherwise noted. table 3. paramete r conditions min typ max unit dynamic performance ? 3 db bandwidth g = +1, v o ut 0.2 v p -p 16.5 19 mhz full power response v o ut = 2 v p -p 5.6 mhz slew rate g = ?1, v o ut = 10 v step 31 35 v/s settling time to 0.1% g = ?1, v o ut = 10 v step 380 ns to 0.01% g = ?1, v o ut = 10 v step 510 ns noise/distortion performance input voltage nois e f = 10 khz 13 nv/hz input current noise f = 1 k hz 1 fa/hz harmonic distortion (sfdr) v o ut = 10 v p - p, f = 20 khz , g = ?1 , r f = r g = 4 k ?101 dbc v out = 10 v p - p, f = 20 k hz, g = +1, r l = 600 ?89 dbc crosstalk f = 1 khz r l = 5 k ?12 3 db f = 1 mhz r l = 5 k ?77 db dc performance initial offset 0.8 3.5 mv maximum offset o ver temperature 1.0 5 mv offset drift 1 v/c input bias current v cm = 0 v 1.3 25 pa v cm = ?10 v 3.5 pa at t max v cm = 0 v 55 95 p a input offset current 1.3 20 pa at t max 9.5 pa open - loop gain v o ut = +10 v to ?10 v, r l = 2 k 100 450 v/mv t min to t max 80 v/mv input characteristics input common - mode vo ltage range ? 15.2 to +13 ? 15.2 to +13.8 v input resistance 10 13 input capacitance differential mode 0.6 pf common mode 1.3 pf common - mo de rejection ratio v cm = ?15 v to +13 v 7 0 90 db output characteristics output voltage swing i l = 100 a ? 14.9 to +14.96 v i l = 2 ma ? 14.97 to +14.9 6 v i l = 10 ma ? 14.9 1 to +14. 89 v linear output current v out = ?14.5 v to +14.5 v 44 ma short - circuit current sourcing to 0 v 78 ma sinking to 0 v 124 ma capacitive load dr ive g = +1 500 pf power supply operating range 3 36 v quiescent current t min to t max , total 6.3 8.4 ma power supply rejection ratio v s = 5 v to 15 v, t min to t max 70 94 db b
ad823a data sheet rev. b | page 6 of 20 absolute maximum ratings table 4. parameter rating supply voltage 36 v power dissipation see figure 4 input voltage (common mode) v s 0.7 v differential input voltage v s output short-circuit duration see figure 4 storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c esd ratings (human body model) 4500 v esd ratings (charged device model) 1250 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. use the part with caution at the 30 v supply as excessive output current may overheat and damage the part. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. the specification is for the device in free air. table 5. thermal resistance package type ja unit 8-lead soic_n 120 c/w 8-lead msop 133 c/w maximum power dissipation (w) ambient temperature (c) 2.0 1.5 0 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 1.0 0.5 t j = 150c 09439-004 8-lead msop 8-lead soic figure 4. maximum power dissipation vs. temperature esd caution
data sheet ad823a rev. | page 7 of 20 pin configuration and function descripti ons ad823 a out1 +in2 ?in2 out2 +v s ?in1 +in1 ?v s 1 2 3 4 8 7 6 5 09439-001 figure 5 . 8 - lead soic pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 out1 output 1. 2 ? in1 inverting input 1. 3 +in1 noninverting input 1. 4 ?v s negative supply. 5 +in2 noni nverting input 2. 6 ? in2 i nverting input 2. 7 out2 output 2. 8 +v s positive supply. 09439-105 out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 out2 7 ?in2 6 +in2 5 ad823a top view (not to scale) figure 6 . 8 - lead msop pin configuration table 7 . pin function descriptions pin no. mnemonic description 1 out1 output 1. 2 ? in1 inverting input 1. 3 +in1 noninverting input 1. 4 ?v s negative supply. 5 +in2 noni nverting input 2. 6 ? in2 i nverting input 2. 7 out2 output 2. 8 +v s positive supply. b
ad823a data sheet rev. | page 8 of 20 typical performance characteristics ?5 ?4 ?3 ?2 ?1 0 1 gain (db) frequency (hz) 1k 10k 100k 1m 10m v s = +5v v out = 0.2v p-p g = +1 09439-005 figure 7 . small signal bandwidth, g = +1 0 10 20 30 40 50 60 70 ?400 ?300 ?200 ?100 0 100 200 300 400 units input offset voltage (v) v s = +5v 350 units = 113v x = 10v 09439-059 figure 8 . typical distribution of input offset voltage 10 20 30 40 50 60 70 80 90 units 0 100 10 input offset voltage drift (v/c) ?4 ?2 0 2 4 6 8 09439-007 v s = +5v ?55c to +125c 240 amplifiers x = 991nv/c = 1.04v/c figure 9 . typi cal distribution of input offset voltage drift 0 2 4 6 8 10 12 14 0 100 200 300 400 500 600 700 800 units input bias current (fa) 09439-009 v s = 2.5v 47 amplifiers = 110fa x = 270fa figure 10 . typical distribution of input bias current 09439-008 ?5 ?4 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 input bias current (pa) common-mode vo lt age (v) v s = +5v figure 11 . input bias current vs. common - mode voltage 0.1 1 10 1000 100 input bias current (pa) temperature (c) 0 25 50 75 100 125 v s = +5v v cm = 0v 09439-010 figure 12 . input bias current vs. temperature b
data sheet ad823a rev. | page 9 of 20 0.1 1 10 100 ?16 ?12 ?8 ?4 0 4 8 12 16 input bias current (pa) common-mode vo lt age (v) v s = 15v 09439-069 figure 13 . input bias current vs. common - mode voltage 80 90 100 1 10 120 0.1 1 10 100 load resis t ance (k) open-loop gain (db) v s = 2.5v 09439-0 11 figure 14 . open - loop gain vs. load resistance 1000 100 10 1 0.1 ?2.5 2.5 ?2.0 2.0 ?1.5 1.5 ?1.0 1.0 ?0.5 0.5 0 open-loop gain (kv/v) output voltage (v) r l = 10k ? r l = 1k ? r l = 100 ? 09439-065 v s = 2.5 v figure 15 . open - loop gain vs. output voltage, v s = 2.5 v ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 100 1k 10k 100k 1m thd (db) frequency (hz) 09439-516 v s = 30v v out = 10v p-p r l = 600 v s = 3v v out = 2v p-p r l = 100 v s = 3v v out = 2v p-p r l = 5k v s = 5v v out = 2v p-p r l = 5k v s = 5v v out = 2v p-p r l = 1k g = ?1 r f = r g = 4k figure16 . total harmonic distortion vs. frequency 99 100 101 102 103 ?55 ?25 5 35 65 95 125 open-loop gain (db) tempera ture ( c) r l = 2k v s = 2.5v 09439-014 figure 17 . open - loop gain vs. temperature ?20 0 20 40 60 80 100 120 ?20 0 20 40 60 80 100 120 1m 10m phase margin (degrees) frequency (hz) 100 1k 10k 100k 100m v s = +5v r l = 2k c l = 20pf open-loop gain (db) phase gain 09439-060 figure 18 . open - loop gain and phase margin vs. frequenc y b
ad823a data sheet rev. | page 10 of 20 10 20 30 40 50 10 100 input voltage noise (nv/hz) frequency (hz) 1k 10k 100k 1m 09439-016 +v s = +5v figure 19 . input voltage noise vs. frequency ?5 ?4 ?3 ?2 ?1 0 1 0.30 3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00 closed-loop gain (db) frequency (mhz) v s = 2.5v c l = 20pf r l = 2k g = +1 +125c ?55c +25c 09439-052 figure 20 . closed - loop bandwidth vs. temperature 0.001 0.01 0.1 1 10 100 output resis t ance () frequenc y (hz) 100 v s = +5v g = +1 1k 10k 100k 1m 10m 09439-053 figure 21 . output resistance vs. frequency, +v s = +5 v, g = +1 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 100 200 300 400 500 600 700 output step size from 0v to v shown (v) settling time (ns) 1% 1% 0.1% 0.1% 0.01% 0.01% v s = 15v c l = 20pf 09439-020 figure 22 . output step size vs. settling time (inverter) 20 30 40 50 60 70 80 90 100 cmrr (db) frequenc y (hz) +v s = +5v 10 100 1k 10k 100k 1m 10m v s = 15v 09439-061 figure 23 . common - mode rejection ratio vs. frequency 0.001 0.01 0.1 1 10 0.1 1 10 100 output saturation voltage (v) load current (ma) +v s = +5v v s to v oh 25c v ol 25c 09439-021 figure 24 . output saturation voltage vs. load current b
data sheet ad823a rev. | page 11 of 20 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 quiescent current (ma) supply voltage (v) 09439-525 ?55c +25c +125c figure 25 . quies cent current vs. supply voltage 100 90 80 70 60 50 40 30 20 10 0 100 10m 1m 100k 10k 1k power supply rejection ratio (db) frequency (hz) 09439-526 +psrr +v s = 5v ?psrr figure 26 . power supply rejection ratio vs. frequency 09439-125 0 5 10 15 20 25 30 10k 100k output voltage (v p-p) frequency (hz) 1m 10m v s = +5v, v in = ?0.2v to +3.8v v s = +3v, v in = ?0.2v to +1.5v r l = 2k g = +1 v s = 15v, v in = ?15.2v to +13.8v figure 27 . large signal frequency response 0 2 4 6 8 10 12 14 16 0 1 2 3 4 5 6 7 8 9 10 capacitance (pf 1000) series resistance (?) +v s = +5v m = 20 m = 45 v in r s c l 09439-067 figure 28 . series resistance vs. capacitive load ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 crosstalk (db) frequency (hz) v s = +5v gain = +1 r l = 2k 1k 10k 100k 1m 10m 09439-063 figure 29 . crosstalk vs. frequency 1.5v 0v 3v 09439-025 10s/div 500mv/div v s = 3v g = ?1 v out = 2.9v p-p figure 30 . output swing, +v s = 1.5 v, g = ?1 b
ad823a data sheet rev. | page 12 of 20 200s/div 500mv/div amplitude (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 09439-328 v s = 5v g = ?1 r f = r g = 2k r l = 300 c l = 50pf figure 31 . output swing, +v s = +5 v, g = ?1 v s = 15v g = +1 v out = 20v p-p r l = 604 ? c l = 50pf 0v 10v ?10v 09439-028 20 s/div 5v/div figure 32 . output swing, v s = 15 v, g = +1 50ns/div 25mv/div 1.55v 1.5v 1.45v 09439-533 v s = 3v g = +1 v in = 100mv step figure 33 . pulse response, +v s = 3 v, g = +1 100ns/div 500mv/div 1v 0v ?1v 09439-048 v s = 5v r l = 2k? c l = 50pf g = +2 v out = 2v p-p figure 34 . pulse response, +v s = 2.5 v, g = +2 100ns/div 500mv/div 4v 2.5v 1v 09439-535 v s = 5v g = +1 v out = 3v p-p r l = 2k c l = 50pf figure 35 . pulse response, +v s = 2.5 v, g = +1 09439-034 200ns/div 500mv/div 2v 3v 2.5v v s = 5v g = +1 r l = 2k? c l = 470pf figure 36 . pulse response, +v s = + 5 v, g = +1, c l = 470 pf b
data sheet ad823a rev. | page 13 of 20 10v ?10v 0v v s = 15v g = +1 r l = 100k c l = 50pf 09439-035 500ns/div 5v/div figure 37 . pulse response, v s = 15 v, g = +1 b
ad823a data sheet rev. | page 14 of 20 theory of operation the ad823a is a dual voltage feedback amplifier with an n-c hannel jfet input stage and a rail - to - rai l bipolar output stage. it is fabricated on the analog devices , inc. xfcb process, a dielectrically isolated complementary bipolar process featuring high speed 36 v bipolar devices along with jfets and thin film resistors. the n - channel input stage handles signals up to 200 mv below the negative supply while maintaining picoamp level input currents. the rail - to - rail output maximizes the amplifiers output range and can provide up to 40 ma linear drive current with output voltages within .5 v of either power rail. laser - trimmed thin film resistors are us ed to optimize offset voltage (3.5 mv max over the entire supply range) and offset voltage drift (typical 1 uv/c). figure 38 shows the architecture of an amplifier . two stages are us ed, with the first stage folded cascode input driving the differential input of the second stage output. the voltage swing at nodes s1p and s1n are kept small to minimize the generation of nonlinear currents due to junction capacitances. this improves dist ortion performance. inputs and outputs of the amplifier are fully protected with dedicated esd diodes. output impedance the low frequency open - loop output impedance of the common - emitter output stage used in this design is approximately 50 k?. although this is significantly higher than a typical emitter follower output stage, when it is connected with feedback, t he open - loop gain of the op amp reduces the output impedance. with 105 db of open - loop gain, the output impedance is reduced to <0.01 ?. at highe r frequencies, the output impedance rises as the open - loop gain of the op amp drops; however, the output also becomes capacitive due to the integrator capacitor . this prevents the output impedance from ever becoming excessively high (see figure 21 ), which can cause stability problems when driving capacitive loads. in fact, the ad823a has excellent capacitive load drive capab ility for a high frequency op amp. figure 36 shows the results of the ad823a connected as a follower while driving a 470 pf direct capacitive load. under these conditions, the phase margin is approximately 35 . for a greater phase margin, use a low value resistor in series with the output to decouple the effect of the load capacitance from the op amp (see figure 28 ). in addition, running the part at higher gains also improves the capacitive load drive capability of the op amp. 09439-138 +v s ?in +in out ?v s v bias s1p s1n output drive figure 38 . simplified schematic b
data sheet ad823a rev. | page 15 of 20 application s information input characteristics in the ad823a , n- channel jfets provide a low offset, low noise, high impedance input stage. minimum input common - mode voltage extends from 0.2 v below ?v s to 1 .2 v < +v s . driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth and increased common - mode voltage error. the ad823a doe s not exhibit phase reversal for input voltages up to and including +v s . figure 39 shows the response of an ad823a voltag e follower to a 0 v to 5 v (+v s ) square wave input. the input and output are superimposed. the output polarity tracks the input polarity up to +v s , with no phase reversal. the reduced bandwidth above a 4 v input causes the rounding of the output wave form. for input voltages greater than +v s , a res istor (r p ) in series with the ad823a noninvertin g i nput prevents phase reversal, at the expense of greater input voltage noi se. the value of r p ranges from 1 k to 10 k. this is illustrated in figure 40 . 2.5v 0v 5.0v 1v 2s 09439-064 input output figure 39 . input and output response: r p = 0 k? , v in = 0 v to +v s 5v v in r p v out ad823a 09439-039 3v 0v 6v 1v 10s input output figure 40 . input and output response: v in = 0 v to +v s + 1 v, v out = 0 v to +v s + 400 mv , r p = 4 .9 9 k? because the input stage uses n - channel jfets, input current during normal operation is negative; the current flows out from the input terminals. if the input voltage is driven more positive than +vs ? 0.7 v, t h e input current reverses direction as internal device junctions become forward biased. this is illustrated in figure 11 . a current limiting resistor should be used in series with the input of the ad823a if the input voltage can be driven over 300 mv more positive than +vs or 300 mv more negative than C vs. the amplifier will be damaged if either condition persists for more than 10 seconds. a 1 k resistor i n series with the ad823a input allows the amplifier to withstand up to 10 v of continuous overvoltage and increases input voltage noise by a negligible amount. the ad823a is designed for 14 nv/hz wideband input voltage noise (see figure 19 ). this noise perf ormance, along with the ad823a low input current and current noise, means that the ad823a contributes negligible noise for applications with high source resistances. figure 41 shows that the source resistance contributes to negligible noise for source impedances lower than 10 k?. the low input capacitance of 0.6 pf also means that one can use a source impedance up to 13 k? without cutting into the g = +1 small signal bandwidth region. noise (nv/ hz) 1 10 10 100 1k 10k 100k 100 09439-338 source resistance () total amplifier noise amplifier voltage and current noise source resistance noise figure 41 . rti noise vs. source resistance output characteristi cs the unique bipolar rail - to - rail output stage of the amplifier swings within 20 mv of th e supplies with no external resistive load. the approximate output saturation resistance of the ad823a is 33 ? sourcing and sinking. this can be used to estimate the output saturation voltage when driving heavier current loads. for instance, when driving 5 ma, the saturation voltage to the rails is approximately 16 5 m v. b
ad823a data sheet rev. | page 16 of 20 wideband photodiode preamp ? + v out v b c d c m c m ad823a r sh = 10 11 ? c s i photo c f r f 09439-055 figure 42 . wideband photodiode preamp the ad823a is an excellent choice for photodiode preamp application. its low input bias current minimizes the dc error at the preamp output. in addition, its hi gh gain bandwidth product and low input capacitance maximizes the signal bandwidth of the photodiode preamp. figure 42 shows the ad823a as a current - to - voltage (i/v) converter with an ele ctrical model of a photodiode. the transimpedance gain of the photodiode preamp can be described by the basic transfer function: ff f photo out r sc ri v + = 1 (1) where i photo is the output current of the photodiode, and the parallel combination of r f and c f se ts the signal bandwidth ( s ee the i to v gain curve in figure 43 ). note that one should set r f such that the maximum attainable output voltage corresponds to the maximum diode current i photo . this allows one to utilize the full outp ut swing . the signal bandwidth that is attainable with this preamp is a function of r f , the gain bandwidth product (f u ) of the amplifier, and the total capacitance at the amplifier summing junction, including c s and the amplifier input capacitance c d and c m . r f and the total capacitance produce a pole with loop frequency (f p ). sf p cr f 2 1 = (2) with the additional pole from the amplifiers open loop response, the two - pole system results in peaking and instability due to an insufficient phase mar gin ( figure 43 (a), without compensation ). adding c f creates a zero in the loop transmission that compensate s for the effect of the input pole. this stabilizes the photodiode preamp design because of the increased p hase margin. it also sets the signal b andwidth ( figure 43 (b), with compensation ). the sig nal bandwidth and the zero frequency are determined by ff z cr f 2 1 = (3) setting the zero at the frequency f x maximi zes the signal bandwidth with a 45 phase ma rgin. since f x is the geometric mean of f p and f u , it can be calculated by up x fff = (4) combining e quation 2, equation 3 and equation 4, the value of c f that produces f x is defined by uf s f fr c c = 2 (5) the frequency response in this case shows about 2 db of peaking and 15% overshoot. doubling c f and cutting the bandwidth in half results in a flat frequency response with about 5% transient overshoot. b
data sheet ad823a rev. | page 17 of 20 log f log f fp g = 1 g = r 2 c 1 s fx fu open-loop gain open-loop gain (a) without compensation f fp g = 1 f fx fu g = 1 + c s /c f fz fn (b) with compensation i to v gain phase () |a| (db) |a (s)| ?180 ?135 ?90 ?45 0 ?135 ?90 ?45 0 45 90 g = r f c s (s) 09439-400 figure 43 . gain and p hase p lot of the t ransimpedance a mplifier d esign the dominant sources of output noise in the wideband photodiode preamp design are the input voltage noise of the amplifier, v noise and the resistor noise due to r f . the gr a y curve in figure 43 shows the noise gain over frequencies for the photodiode preamp. the noise bandwidth is at the frequency f n , and it can be calculated by ( ) ffs u n ccc f f + = (6) figure 44 shows the ad823a configured as a transimpedance photodiode amplifier. the amplifier is used in conjunction with a photodiode detector with input capacitance of 5 pf. figure 45 shows the transimpedance response of the ad823a when i photo is 1 a p - p. the amplifier has a bandwidth of 2.2 mhz when it is maximized for a 45 phase margin with c f = 1.2 pf. note that with the pcb parasitics added to c f , the peaking is only 0.5 db and the bandwidth is slightly reduced. increasing c f to 2.7 pf completely eliminates the peaking. however, it reduces the bandwidth to 1.2 mhz. table 8 shows the noise sources and total output noise for the photodiode preamp, where t he preamplifier is configured to have a 45 phase margin for maximal bandwidth and f z = f x = f n in this case. ad823a 0.1 f +5v 49.9k? v out 0.1 f ?5v ?5v 100 ? 1.2pf 09439-050 figure 44 . photodiode preamplifier 95 85 86 87 88 89 90 91 92 93 94 1k 10k 100k 1m 10m transimpedance gain (db) frequency (hz) 09439-144 i photo = 1a p-p c f = 1.2pf i photo = 1a p-p c f = 2.7pf figure 45 . photodiode preamplifier frequency response b
ad823a data sheet rev. b | page 18 of 20 table 8. rms noise contributions of photodiode preamp contributor expression (v) 1 r f 2 ??? nf fr4kt 55.17 v noise ?? n f d fms noise f c 2cccc v ?? ??? ? 2 138.5 rss total 149.1 1 rms noise with r f = 50 k, c s = 5 pf, c f = 1.2 pf, c m = 1.3 pf, and c d = 0.6 pf. active filter the ad823a is an ideal candidate for an active filter because of its low input bias current and its low input capacitance. low input bias current reduces dc error in the signal path while low input capacitance improves the accuracy of the active filter. as a general rule of thumb, the bandwidth of the amplifier should be at least 10 times bigger than the cutoff frequency of the filter implemented. therefore, the ad823a is capable of implementing active filters of up to 1.7 mhz. 0 9439-146 ad823a r t 49.9 ? r2 1.12k ? r1 1.12k ? c1 200pf +v s ?v s v out v in c2 100pf figure 46. two-pole sallen-key active filter figure 46 shows an example of a second-order butterworth filter, which is implemented by the sallen-key topology. this structure can be duplicated to produce higher-order filters. 3 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 100 1k 10k 100k 10m 1m magnitude (db) frequency (hz) 09439-147 figure 47. two-pole butterworth active filter response figure 47 shows the two-pole butterworth active filters response. note that it has a maximally flat pass band, a ?3 db bandwidth of 1 mhz, and a 12 db/octave roll-off in the stop band. the cutoff frequency (f c ) and the q factor of the butterworth filter can be calculated by: 2121 2 1 ccrr f c ? ? (7) ?? 221 2121 crr ccrr q ?? ? (8) therefore, one can easily adjust the cutoff frequency by appropriately factoring the resistor and capacitor values. for example, a 100 khz filter can be implemented by increasing the values of r1 and r2 by 10 times. note that the q factor remains the same in this case.
data sheet ad823a rev. | page 19 of 20 maximizing performan ce through proper layout to achieve the maximum perform ance of the extremely high input impedance and low offset voltage of the ad823a , care should be taken in the circuit board layout. the pcb surface must remain clean and free of moisture to avoid leakage current s between adjacent traces. surface coating of the circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. the use of guard rings around the amplifier inputs further reduces lea kage currents. figure 48 shows how the guard ring s should be configured, and figure 49 shows the top view of how a surface - mount layout can be arranged. the guard ring does not need to be a specific width, but it should for m a continuous loop around both inputs. by setting the guard ring voltage equal to the voltage at the non - inverting input, parasitic capacitance is minimized as well. for further reduction of leakage currents, components can be mounted to the pcb using tefl on ? standoff insulators. v out v out v out v in ad823a v in ad823a v in ad823a 09439-152 figure 48 . guard ring layout and connections to reduce pcb leakage currents v? v+ v ref v ref v in1 v in2 guard ring r1 r2 r2 r1 ad823a guard ring 09439-153 figure 49 . top view of ad 823a soic layout with guard rings b
ad823a data sheet rev. b | page 20 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 50. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 51. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide models 1 temperature range package description package option branding ad823aarz ?40c to +85c 8-lead soic_n r-8 ad823aarz-rl ?40c to +85c 8-lead soic_n, 13 tape and reel r-8 ad823aarz-r7 ?40c to +85c 8-lead soic_n, 7 tape and reel r-8 AD823AARMZ ?40c to +85c 8-lead msop rm-8 h34 AD823AARMZ-r7 ?40c to +85c 8-lead msop, 7 tape and reel rm-8 h34 ad823a-2ar-ebz evaluation board for 8-lead soic ad823a-2arm-ebz evaluation board for 8-lead msop 1 z = rohs compliant part. ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09439-0-6/12(b)

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